1. Field of the Invention
The present invention relates to the field of microprocessor design. Specifically, the present invention relates to a method for analyzing the power expenditure of microprocessor designs at the architectural level, including accurate estimation of maximum power consumption.
2. Related Art
Performance requirements have pushed microprocessor complexity to millions of devices per chip, and clock rates into the GHz range. Consequent microprocessor power consumption is outpacing gains from advances and scaling in silicon technologies, and benefits of reduced power supply voltages. Thus, power consumption is a major issue in microprocessor design, and reducing power consumption without adversely affecting performance is a major challenge. Conventional Art FIG. 1 illustrates this situation for contemporary personal computer and workstation processor architectures.
The power consumption issue affects almost every aspect of the initial architecture, ultimate performance, and overall utility of processors. From a system design perspective, processor maximum power consumption is much more useful than average power consumption. Beside criteria specific to the processor itself, this is also related to infrastructure specifications, cooling for example, which are designed primarily to accommodate the maximum processor power dissipation.
Maximum power consumption of microprocessors is either measured experimentally from real chips, or calculated when the processor design is approaching completion. Conventionally, these determinations are based on switching activities in the processor. A typical analytical method of the conventional art may apply a special set of instruction streams, for example, a xe2x80x9cpower virus,xe2x80x9d to run a processor in maximum power consumption mode.
One such computation, based on the switched capacitance of every node in the processor, can be expressed by
P=CV2fA
where A is the activity of all nodes in the processor when running a maximum power virus code, C is the node FET capacitance adjusted to compensate for average static current and correlated with artwork based SPICE results including wire capacitance, V is the supply voltage, and f is the processor frequency. There are also, in the conventional art, commercially available implementation level power estimation tools such as the Sente WattWatcher(trademark) of Sente, Inc. of Acton, Mass. These are full chip power analysis tools for the system-on-chip designs, usable at both the register-transfer and gate levels.
Conventionally, architectural level power estimation for processors is empirically based on implementation level measurements; the power consumption of existing functional unit implementations is measured and models are produced based on those measurements. Such conventional approaches include fixed activity macromodeling, activity-sensitive macromodeling, and transition-sensitive macromodeling. Another approach imitates the behavior of the processor with previously characterized energy consumption of its functional units. All of the foregoing conventional methods are implementation-constrained; they all need some form of past implementation data at the functional unit level to estimate processor power dissipation. Hence they limit the freedom to experiment with architectural tradeoffs to evaluate various power management techniques.
While these assessments are available at the implementation level, processor architecture has by then already been defined; they are ineffective in initial design. To effectively design power efficient processors, knowledge of their power consumption behavior early in the architectural definition stage is essential. Few such methods are available for analyzing power consumption at this architectural level. But comprehension of the processor""s power consumption behavior early in the architectural definition stage of processor design is essential to minimizing power consumption without concomitantly curtailing its subsequent (e.g., post-implementation) performance.
For example, power efficiency for each of the example processor architectures in Conventional Art FIG. 1 can be calculated based on the Horowitz equation, well known in the art,
Power Efficiency=1/(Energy)(Delay)=SPEC2/Watt
where SPEC is the appropriate Standard Performance Evaluation Corporation benchmark rating for each listed processor (SPEC, Warrenton, Va.). Conventional Art FIG. 2 summarizes the maximum power efficiencies of these processor architectures, relative to each other, for both SPECint and SPECfp performance (e.g., SPEC integer and floating point performance ratings, respectively), although the SPEC benchmarks, by themselves, may not represent maximum power dissipation for these processors.
Knowing such power performance behavior for microprocessors during their architectural definition stages, prior to commitment to implementation, would be invaluable for making appropriate architectural feature choices for intended application spaces. For example, floating point power efficiency information is useful in tuning the architecture for either PC or workstation applications. In fact, from Conventional Art FIG. 2, the processors intended primarily for the PC applications (AMD Athlon(trademark), Intel PIII(trademark), and PowerPC 7400(trademark)) do show lower power efficiency for SPECfp than for SPECint, whereas the rest of the processors, primarily intended for workstation type applications, show higher power efficiencies for SPECfp than for SPECint.
Architectural solutions or enhancements for power-aware behavior of processors proposed in the conventional art include complexity adaptive processors, instruction scheduling for low power, dynamically reconfigurable functional units, optimizations to the cache hierarchy, and techniques to reduce bus energy. Many of these proposed solutions will require architectural level power estimation to evaluate their relative benefits from a power perspective.
It is conceivable that a power consumption estimation scheme may be developed for each individual processor to be designed, analyzing maximum power criteria prior to implementation. Developing such a scheme may be incorporated into the initial architectural process of each new processor, or at best, related group of similar processors. However, this would probably be expensive, repetitive, and wasteful.
The conventional art is problematic because the field as currently practiced applies only at the post-architectural stage implementation level, generally considers only average power, and applies only to specific designs.
What is needed is a new method for estimating the power consumption in a microprocessor. What is also needed is a method for estimating the power consumption in microprocessors, which is applied in initial architectural stage during the design of microprocessors, before expenditure of resources is committed to the implementation of real devices. Further, what is needed is a method for estimating the power consumption in a microprocessor which applies analysis based on maximum power dissipation by the processor. Further still, what is needed is a method achieving the foregoing accomplishments which is applicable to any microprocessor architecture under design.
The present invention provides a novel method for estimating the power consumption in a microprocessor, other integrated circuit, or system. The present invention also provides a method for estimating the power consumption in microprocessors, which is applied in initial architectural stages, during the design of microprocessors, before expenditure of resources is committed to the implementation of real devices. Further, the present invention provides a method for estimating the power consumption in a microprocessor, which applies analysis based on maximum power dissipation by the processor. Further still, the present invention provides a method achieving the foregoing accomplishments, applicable to any microprocessor architecture under design.
In one embodiment, the present invention, provides a novel method for estimating the power consumption in a microprocessor. In one embodiment, the method is applicable not only to microprocessors, but to any other integrated circuit or to entire systems, including, but not limited to computer systems. In one embodiment, maximum power dissipation estimates are assessed at a pre-implementation architectural level applicable to any architecture.
In one embodiment of the present invention, a method for estimating the power consumption in microprocessors is applied in architectural stages, during the design of microprocessors, before expenditure of resources is committed to the implementation of real devices. Power estimation for a processor at the architectural level is a complex problem. At this stage of processor design, conceptual ideas are being evaluated, and implementation details are not yet available. Power consumption, on the other hand, is very much dependent on implementation. An innovative method of architectural modeling in the present embodiment enables power estimation to be within reasonable margins of errors.
In one embodiment, the present invention provides a method for estimating the power consumption in a microprocessor, which applies analysis. based on maximum power dissipation by the processor. In the present embodiment, a high level model of the processor receives power weights based on actual technology parameters added to every step of every use of processor functions, a benchmark program runs the processor in its maximum power consumption mode, an instruction stream to exercise the model is produced, and total power consumption and that of each architectural function is summarized.
In one embodiment, the present invention provides a method achieving the foregoing accomplishments, applicable to any microprocessor architecture, other integrated circuit (IC) architecture (including application specific ICs), or system, including computer systems, under design. In the present embodiment, maximum power efficiency of PC, workstation, and other processors, other integrated circuits, and systems is separated from the architectural component and the technology component of processor power estimation and analysis. This approach provides complete freedom to perform power-aware architectural experiments using behavioral level simulations for any processor, without interference or slow-down due to the implementation technology parameters.
These and other objects and advantages of the present invention will become obvious to those of ordinary skill in the at after reading the following detailed description of the preferred embodiments which are illustrated in the drawing figures.